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<title>SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords </title></head>
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<h1>SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 38 CD /r</p>
<p>SHA256MSG2 xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>SHA</td>
<td>Performs the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the final calculation for the next four SHA256 message dwords.</p>
<p><strong>Operation</strong></p>
<p><strong>SHA256MSG2</strong></p>
<p>W14 (cid:197) SRC2[95:64] ;</p>
<p>W15 (cid:197) SRC2[127:96] ;</p>
<p>W16 (cid:197) SRC1[31: 0] + σ<sub>1</sub>( W14) ;</p>
<p>W17 (cid:197) SRC1[63: 32] + σ<sub>1</sub>( W15) ;</p>
<p>W18 (cid:197) SRC1[95: 64] + σ<sub>1</sub>( W16) ;</p>
<p>W19 (cid:197) SRC1[127: 96] + σ<sub>1</sub>( W17) ;</p>
<p>DEST[127:96] (cid:197) W19 ;</p>
<p>DEST[95:64] (cid:197) W18 ;</p>
<p>DEST[63:32] (cid:197) W17 ;</p>
<p>DEST[31:0] (cid:197) W16;</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>SHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);</p>
<p><strong>Flags Affected</strong></p>
<p>None</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type 4.</p></body></html>